In recent years, there has been an increasing demand for smaller semiconductor devices that can be used as non-volatile memory media for portable electronic devices such as portable telephone devices and IC memory cards. In this trend, techniques of efficiently packaging semiconductor chips have been developed. As one of such techniques, there is a method of packaging stacked semiconductor chips.
Japanese Patent Application Publication No. 2004-342861 discloses the following technique (conventional technique 1). Firstly, grooves are formed on the upper face of a semiconductor wafer, and an insulating layer is embedded in the grooves. Through holes having conductors embedded therein are then formed in the insulating layer. The through holes are cut so as to divide the semiconductor wafer into semiconductor chips. The through holes become concavities formed on the side faces of the semiconductor chip, and the conductors formed in the through holes electrically connect the upper face and the lower face of the semiconductor chip.
Japanese Patent Application Publication No. 2004-221372 discloses the following technique (conventional technique 2). Through holes having side walls covered with conductors are formed in a semiconductor wafer. The through holes are cut so as to divide the semiconductor wafer into semiconductor chips. The semiconductor chips are stacked, and metal resin layers are formed in the concavities formed from the through holes in the side faces of the semiconductor chips. The stacked semiconductor chips are electrically connected to one another via the metal resin layers formed in the concavities.
Japanese Patent Application Publication No. 2001-250906 discloses the following technique (conventional technique 3). After semiconductor chips are stacked, wiring patterns are formed on the side faces of the stacked semiconductor chips. The stacked semiconductor chips are electrically connected to one another via the wiring patterns.
As in the conventional technique 1 and the conventional technique 2, however, the following problems are caused in a case where through holes are formed in a semiconductor wafer and are cut to divide the semiconductor wafer into semiconductor chips. Since the conductors that are embedded in the through holes or cover the side walls of the through holes are cut, the conductors are likely to come off when the wafer is divided into chips. Also, to form through holes in a semiconductor wafer or an insulating layer, deep etching needs to be performed. This is technologically difficult, and results in higher production costs. In the conventional technique 3, wiring patterns are formed in semiconductor chips after the semiconductor chips are stacked. As a result, the production costs become higher.